View AD8002ARZ_3978003.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

rev. d information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of analog devices. a ad8002 one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 781/329-4700 world wide web site: www.analog.com fax: 781/326-8703 ? analog devices, inc., 2001 dual 600 mhz, 50 mw current feedback amplifier features excellent video specifications (r l = 150 , g = +2) gain flatness 0.1 db to 60 mhz 0.01% differential gain error 0.02 differential phase error low power 5.5 ma/amp max power supply current (55 mw) high speed and fast settling 600 mhz, C3 db bandwidth (g = +1) 500 mhz, C3 db bandwidth (g = +2) 1200 v/ s slew rate 16 ns settling time to 0.1% low distortion C65 dbc thd, f c = 5 mhz 33 dbm third order intercept, f 1 = 10 mhz C66 db sfdr, f = 5 mhz C60 db crosstalk, f = 5 mhz high output drive over 70 ma output current drives up to eight back-terminated 75 loads (four loads/side) while maintaining good differential gain/phase performance (0.01%/0.17 ) available in 8-lead plastic dip, soic and soic packages applications a-to-d driver video line driver differential line driver professional cameras video switchers special effects rf receivers functional block diagram 8-lead plastic dip, soic, and soic out1 ?n1 +in1 v v+ out2 ?n2 +in2 1 2 3 4 8 7 6 5 ad8002 product description the ad8002 is a dual, low-power, high-speed amplifier des igned to operate on 5 v supplies. the ad8002 features unique trans- impedance linearization circuitry. this allows it to drive video loads with excellent differential gain and phase performance on only 50 mw of power per amplifier. the ad8002 is a current feedback amplifier and features gain flatness of 0.1 db to 60 mhz while offering differential gain and phase error of 0.01% and 0.02 . this makes the ad8002 ideal for professional video electronics such as cameras and video switchers. additionally, the ad8002? low distortion and fast settling make it ideal for buffer high-speed a-to-d converters. the ad8002 offers low power of 5.5 ma/amplifier max (v s = 5 v) and can run on a single 12 v power supply, while capable of delivering over 70 ma of load current. it is offered in an 8-lead plastic dip, soic, and soic package. these features make this amplifier ideal for portable and battery-powered applica tions where size and power are critical. the outstanding bandwidth of 600 mhz along with 1200 v/ s of slew rate make the ad8002 useful in many general purpose high speed applications where dual power supplies of up to 6 v and single supplies from 6 v to 12 v are needed. the ad8002 is available in the industrial temperature range of ?0 c to +85 c. 1m 10m 1g 100m 0 0.5 0.1 0.2 0.3 0.4 0.1 1 4 9 5 6 7 8 3 2 1 0 normalized flatness db frequency hz normalized frequency response db side 1 side 2 side 1 side 2 g = +2 r l = 100 v in = 50mv figure 1. frequency response and flatness, g = +2 g = +2 1v step side 1 200mv side 2 5ns figure 2. 1 v step response, g = +1
rev. d C2C ad8002?pecifications (@ t a = 25 c, v s = 5 v, r l = 100 , r c 1 = 75 , unless otherwise noted.) model ad8002a conditions min typ max unit dynamic performance ? db small signal bandwidth, n package g = +2, r f = 750 ? 500 mhz g = +1, r f = 1.21 k ? 600 mhz r package g = +2, r f = 681 ? 500 mhz g = +1, r f = 953 ? 600 mhz rm package g = +2, r f = 681 ? 500 mhz g = +1, r f = 1 k ? 600 mhz bandwidth for 0.1 db flatness n package g = +2, r f = 750 ? 60 mhz r package g = +2, r f = 681 ? 90 mhz rm package g = +2, r f = 681 ? 60 mhz slew rate g = +2, v o = 2 v step 700 v/ s g = ?, v o = 2 v step 1200 v/ s settling time to 0.1% g = +2, v o = 2 v step 16 ns rise and fall time g = +2, v o = 2 v step, r f = 750 ? 2.4 ns noise/harmonic performance total harmonic distortion f c = 5 mhz, v o = 2 v p-p ?5 dbc g = +2, r l = 100 ? crosstalk, output to output f = 5 mhz, g = +2 ?0 db input voltage noise f = 10 khz, r c = 0 ? 2.0 nv/ hz input current noise f = 10 khz, +in 2.0 pa/ hz ?n 18 pa/ hz differential gain error ntsc, g = +2, r l = 150 ? 0.01 % differential phase error ntsc, g = +2, r l = 150 ? 0.02 degree third order intercept f = 10 mhz 33 dbm 1 db gain compression f = 10 mhz 14 dbm sfdr f = 5 mhz ?6 db dc performance input offset voltage 2.0 6 mv t min ? max 2.0 9 mv offset drift 10 v/ c ?nput bias current 5.0 25 a t min ? max 35 a +input bias current 3.0 6.0 a t min ? max 10 a open loop transresistance v o = 2.5 v 250 900 k ? t min ? max 175 k ? input characteristics input resistance +input 10 m ? ?nput 50 ? input capacitance +input 1.5 pf input common-mode voltage range 3.2 v common-mode rejection ratio offset voltage v cm = 2.5 v 49 54 db ?nput current v cm = 2.5 v, t min ? max 0.3 1.0 a/v +input current v cm = 2.5 v, t min ? max 0.2 0.9 a/v output characteristics output voltage swing r l = 150 ? 2.7 3.1 v output current 2 70 ma short circuit current 2 85 110 ma power supply operating range 3.0 6.0 v quiescent current/both amplifiers t min ? max 10.0 11.5 ma power supply rejection ratio +v s = +4 v to +6 v, ? s = ? v 60 75 db ? s = 4 v to 6 v, +v s = +5 v 49 56 db ?nput current t min ? max 0.5 2.5 a/v +input current t min ? max 0.1 0.5 a/v notes 1 r c is recommended to reduce peaking and minimize input reflections at frequencies above 300 mhz. however, r c is not required. 2 output current is limited by the maximum power dissipation in the package. see the power derating curves. specifications subject to change without notice.
rev. d ad8002 C3C absolute maximum ratings 1 supply voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13.2 v internal power dissipation 2 plastic dip package (n) . . . . . . . . . . . . . . . . . . . . . . . 1.3 w small outline package (r) . . . . . . . . . . . . . . . . . . . . . . 0.9 w soic package (rm) . . . . . . . . . . . . . . . . . . . . . . . . . 0.6 w input voltage (common mode) . . . . . . . . . . . . . . . . . . . . v s differential input voltage . . . . . . . . . . . . . . . . . . . . . . . 1.2 v output short circuit duration . . . . . . . . . . . . . . . . . . . . . . observe power derating curves storage temperature range n, r, rm . . . . . ?5 c to +125 c operating temperature range (a grade) . . . 40 c to +85 c lead temperature range (soldering 10 sec) . . . . . . . . . 300 c notes 1 stresses above those listed under absolute maximum ratings may cause perma- nent damage to the device. this is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. 2 specification is for device in free air: 8-lead plastic dip package: ja = 90 c/w 8-lead soic package: ja = 155 c/w 8-lead soic package: ja = 200 c/w maximum power dissipation the maximum power that can be safely dissipated by the ad8002 is limited by the associated rise in junction tempera- ture. the maximum safe junction temperature for plastic encapsulated devices is determined by the glass transition tem- perature of the plastic, approximately 150 c. exceeding this limit temporarily may cause a shift in parametric performance due to a change in the stresses exerted on the die by the package. exceeding a junction temperature of 175 c for an extended period can result in device failure. while the ad8002 is internally short circuit protected, this may not be sufficient to guarantee that the maximum junction temperature (150 c) is not exceeded under all conditions. to ensure proper operation, it is necessary to observe the maximum power derating curves. 2.0 0 50 80 1.5 0.5 40 1.0 010 10 20 30 20 30 40 50 60 70 90 maximum power dissipation w ambient temperature c 8-lead plastic-dip package 8-lead soic package t j = 150 c 8-lead soic package figure 3. plot of maximum power dissipation vs. temperature caution esd (electrostatic discharge) sensitive device. electrostatic charges as high as 4000 v readily accumulate on the human body and test equipment and can discharge without detection. although the ad8002 features proprietary esd protection circuitry, permanent damage may occur on devices subjected to high-energy electrostatic discharges. therefore, proper esd precautions are recommended to avoid performance degradation or loss of functionality. ordering guide model temperature range package description package option brand code ad8002an ?0 c to +85 c 8-lead pdip n-8 standard ad8002ar ?0 c to +85 c 8-lead soic so-8 standard ad8002ar-reel ?0 c to +85 c 8-lead soic 13" reel so-8 standard ad8002ar-reel7 ?0 c to +85 c 8-lead soic 7" reel so-8 standard ad8002arm ?0 c to +85 c 8-lead soic rm-8 hfa ad8002arm-reel ?0 c to +85 c 8-lead soic 13" reel rm-8 hfa ad8002arm-reel7 ?0 c to +85 c 8-lead soic 7" reel rm-8 hfa warning! esd sensitive device
rev. d ad8002 C4C pulse generator 953 +5v r l = 100 5v 50 v in 0.1 f 10 f ad8002 0.1 f 10 f t r /t f = 250ps 75 tpc 1. test circuit , gain = +1 g = +1 100mv step side 1 20mv side 2 5ns tpc 2. 100 mv step response, g = +1 g = +1 1v step side 1 200mv side 2 5ns tpc 3. 1 v step response, g = +1 typical performance characteristics pulse generator 750 +5v r l = 100 5v 50 v in 0.1 f 10 f ad8002 0.1 f 10 f t r /t f = 250ps 75 750 tpc 4. test circuit, gain = +2 g = +2 100mv step side 1 20mv side 2 5ns tpc 5. 100 mv step response, g = +2 g = +2 1v step side 1 20mv side 2 5ns tpc 6. 1 v step response, g = +2
rev. d ad8002 C5C 1m 10m 1g 100m 0 0.5 0.1 0.2 0.3 0.4 0.1 1 4 9 5 6 7 8 3 2 1 0 normalized flatness db frequency hz normalized frequency response db g = +2 r l = 100 v in = 50mv side 1 side 2 side 1 side 2 75 50 50 r f 681 681 tpc 7. frequency response and flatness, g = +2 frequency hz 50 60 distortion dbc 110 10k 100m 100k 1m 10m 70 80 100 90 2nd harmonic 3rd harmonic g = +2 r l = 100 tpc 8. distortion vs. frequency, g = +2, r l = 100 ? frequency hz 60 distortion dbc 110 10k 100m 100k 1m 10m 70 80 100 90 2nd harmonic 3rd harmonic g = +2 r l = 1k v out = 2v p-p 120 tpc 9. distortion vs. frequency, g = +2, r l = 1 k ? 70 1m 100m 10m 100k 60 100 90 80 output side 1 output side 2 crosstalk db 50 40 30 20 110 120 frequency hz v in = 4dbv r l = 100 v s = 5.0v g = +2 r f = 750 tpc 10. crosstalk (output-to-output) vs. frequency notes: side 1: v in = 0v; 8mv/div rto side 2: 1v step rto; 400mv/div g = + 2 r f = 750 r c = 75 r l = 100 side 1 side 2 5ns tpc 11. pulse crosstalk, worst case, 1 v step 0.02 0.06 0.02 1 0.04 0.02 0.08 0.01 0.00 0.01 ire diff gain % diff phase degrees 0.00 g = +2 r f = 750 ntsc 234567891011 2 back-terminated loads (75 ) 1 back-terminated load (150 ) 2 back-terminated loads (75 ) 1 back-terminated load (150 ) tpc 12. differential gain and differential phase (per amplifier)
rev. d ad8002 C6C 2 1 4 3 0 1 2 5 6 10m 1g 100m 1m frequency hz gain db side 1 side 2 75 50 50 953 v in = 50mv g = +1 r f = 953 r l = 100 tpc 13. frequency response, g = +1 40 70 100 80 90 60 50 100k 100m 10m 1m 10k frequency hz distortion dbc g = +1 r l = 100 v out = 2v p-p 2nd harmonic 3rd harmonic tpc 14. distortion vs. frequency, g = +1, r l = 100 ? 40 60 110 50 80 70 100 90 100k 100m 10m 1m 10k frequency hz distortion dbc g = +1 r l = 1k 3rd harmonic 2nd harmonic tpc 15. distortion vs. frequency, g = +1, r l = 1 k ? 0 3 27 10m 500m 100m 18 21 24 15 12 9 6 input level dbv frequency hz 6 3 0 3 6 9 12 15 18 21 output level dbv 1m g = +2 r f = 681 v s = 5v r l = 100 tpc 16. large signal frequency response, g = +2 input/output level dbv frequency hz 6 3 27 12 15 18 9 6 3 0 9 10m 500m 100m 1m r l = 100 g = +1 r f = 1.21k 75 50 50 1.21k tpc 17. large signal frequency response, g = +1 25 10 5 1m 10m 100m 0 5 15 20 frequency hz gain db 1g 45 30 35 40 g = +100 r f = 1000 g = +10 r f = 499 v s = 5v r l = 100 tpc 18. frequency response, g = +10, g = +100
rev. d ad8002 C7C g = +2 2v step r f = 750 r c = 75 output error, (0.05%/div) input 10ns 400mv tpc 19. short-term settling time 3.4 2.5 125 2.7 2.6 35 55 2.8 2.9 3.0 3.1 3.2 3.3 105 85 65 45 25 5 15 junction temperature c output swing volts +v out | v out | v s = 5v r l = 150 +v out | v out | v s = 5v r l = 50 tpc 20. output swing vs. temperature 5 3 1 2 1 0 2 3 4 125 35 55 105 85 65 45 25 5 15 junction temperature c input bias current a in +in tpc 21. input bias current vs. temperature error, (0.05%/div) g = +2 2v step r f = 750 r c = 75 r l = 100 output input 400mv tpc 22. long-term settling time 4 3 0 2 1 3 1 2 125 35 55 105 85 65 45 25 5 15 junction temperature c input offset voltage mv device #1 device #2 device #3 .+0'* :
. 11.5 9.0 125 10.5 9.5 35 10.0 55 11.0 105 85 65 45 25 5 15 junction temperature c total supply current ma v s = 5v tpc 24. total supply current vs. temperature
rev. d ad8002 C8C 120 75 125 85 80 35 55 90 95 100 105 110 115 105 85 65 45 25 5 15 junction temperature c short circuit current ma |sink i sc | source i sc 70 tpc 25. short circuit current vs. temperature 100 10 1 10 100 100k 10k 1k frequency hz 100 10 1 noise voltage nv/ hz noise current pa/ hz inverting current v s = 5v noninverting current v s = 5v voltage noise v s = 5v tpc 26. noise vs. frequency 48 56 54 55 52 53 51 50 49 125 35 55 105 85 65 45 25 5 15 junction temperature c cmrr db cmrr +cmrr tpc 27. cmrr vs. temperature frequency hz 1 10k 100k 1g 100m 10m 1m 10 100 0.01 0.1 resistance r f = 750 r c = 75 v s = 5.0v power = 0dbm (223.6mvrms) g = +2 r bt = 0 r bt = 50 tpc 28. output resistance vs. frequency 1 4 9 1m 10m 1g 100m 5 6 7 8 3 2 1 0 frequency hz output voltage db 0 0.1 0.2 0.3 0.1 0.2 3db bandwidth 0.1db flatness side 1 side 1 side 2 side 2 v s = 5v v in = 50mv g = 1 r l = 100 r f = 549 .+0'7 )*>> !#$%)" 50.0 72.5 125 67.5 70.0 35 55 65.0 62.5 60.0 57.5 55.0 52.5 105 85 65 45 25 5 15 junction temperature c psrr db 75.0 psrr +psrr 2v span curves are for worst- case condition where one supply is varied while the other is held constant. tpc 30. psrr vs. temperature
rev. d ad8002 C9C 100m 10m 1m frequency hz 40 30 cmrr db 1g 50 60 20 10 0 604 v in 154 154 604 50 57.6 5v 0.1 f v s = 5.0v r l = 100 v in = 200mv side 1 side 2 tpc 31. cmrr vs. frequency g = 1 r f = 576 r g = 576 r c = 50 5ns 400mv side 1 side 2 tpc 32. 2 v step response, g = C1 54.9 50 50 576 576 g = 1 r f = 576 r g = 576 r c = 50 r l = 100 5ns 20mv side 1 side 2 tpc 33. 100 mv step response, g = C1 20 50 100k 1m 10m 40 30 10 frequency hz psrr db 90 80 70 60 100m 0 30k 500m +psrr psrr v in = 200mv g = +2 .+0*/ +(!# g = 2 2v step r f = 549 5ns 400mv side 1 side 2 tpc 35. 2 v step response, g = C2 61.9 50 50 549 274 g = 1 100mv step r f = 549 5ns 20mv side 1 side 2 tpc 36. 100 mv step response, g = C2
rev. d ad8002 C10C theory of operation a very simple analysis can put the operation of the ad8002, a current feedback amplifier, in familiar terms. being a current feedback amplifier, the ad8002? open-loop behavior is expressed as transimpedance, ? v o / ? i ?n , or t z . the open-loop transim- pedance behaves just as the open-loop voltage gain of a voltage feedback amplifier, that is, it has a large dc value and decreases at roughly 6 db/octave in frequency. since the r in is proportional to 1/g m , the equivalent voltage gain is just t z g m , where the g m in question is the trans- conductance of the input stage. this results in a low open-loop input impedance at the inverting input, a now familiar result. using this amplifier as a follower with gain, figure 4, basic analysis yields the following result. v v g ts ts gr r g r r rg o in z zin in m = + + =+ = () () / 1 1 1 2 150 ? v out r1 r2 r in v in figure 4. recognizing that g r in << r1 for low gains, it can be seen to the first order that bandwidth for this amplifier is independent of gain (g). considering that additional poles contribute excess phase at high frequencies, there is a minimum feedback resistance below which peaking or oscillation may result. this fact is used to determine the optimum feedback resistance, r f . in practice parasitic capacitance at the inverting input terminal will also add phase in the feedback loop, so picking an optimum value for r f can be difficult. achieving and maintaining gain flatness of better than 0.1 db at frequencies above 10 mhz requires careful consideration of several issues. choice of feedback and gain resistors the fine scale gain flatness will, to some extent, vary with feedback resistance. it, therefore, is recommended that once optimum resistor values have been determined, 1% tolerance values should be used if it is desired to maintain flatness over a wide range of production lots. in addition, resistors of different construction have different associated parasitic capacitance and i nductance. surface mount resistors were used for the bulk of the characterization for this data sheet. it is not recommended that leaded components be used with the ad8002. printed circuit board layout considerations as expected for a wideband amplifier, pc board parasitics can affect the overall closed-loop performance. of concern are stray capacitances at the output and the inverting input nodes. if a ground plane is to be used on the same side of the board as the signal traces, a space (5 mm min) should be left around the signal lines to minimize coupling. additionally, signal lines connecting the feedback and gain resistors should be short enough so that their associ ated inductance does not cause high frequency gain errors. line lengths on the order of less than 5 mm are recommended. if long runs of coaxial cable are being driven, dispersion and loss must be considered. power supply bypassing adequate power supply bypassing can be critical when optimiz- ing the performance of a high-frequency circuit. inductance in the power supply leads can form resonant circuits that produce peaking in the amplifier s response. in addition, if large current transients must be delivered to the load, bypass capacitors (typically greater than 1 f) will be required to provide the best settling time and lowest distortion. a parallel combina- tion of 4.7 f and 0.1 f is recommended. some brands of electrolytic capacitors will require a small series damping resis- tor 4.7 ? for optimum results. dc errors and noise there are three major noise and offset terms to consider in a current feedback amplifier. for offset errors, refer to the equa- tion below. for noise error, the terms are root-sum-squared to give a net output error. in the circuit shown in figure 5 they are input offset (v io ), which appears at the output multiplied by the noise gain of the circuit (1 + r f /r i ), noninverting input current (i bn r n ), also multiplied by the noise gain, and the inverting input current, which, when divided between r f and r i and subsequently multiplied by the noise gain, always appears at the output as i bn r f . the input voltage noise of the ad8002 is a low 2 nv/ hz . at low gains, though, the inverting input current noise times r f is the dominant noise source. careful layout and device matching contribute to better offset and drift specifi cations for the ad8002 com pared to many other current feed back amplifiers. the typical performance curves in conjunction with the equations below can be used to predict the performance of the ad8002 in any application. vv r r ir r r ir out io f i bn n f i bi f =+ ? ? ? ? ? ? + ? ? ? ? ? ? 11 r f r i r n i bn v out i bi figure 5. output offset voltage
rev. d ad8002 C11C driving capacitive loads the ad8002 was designed primarily to drive nonreactive loads. if driving loads with a capacitive component is desired, best frequency response is obtained by the addition of a small series resistance as shown in figure 6. 909 r series r l 500 i n c l figure 6. driving capacitive loads figure 7 shows the optimum value for r series versus capacitive load. it is worth noting that the frequency response of the circuit when driving large capacitive loads will be dominated by the passive roll-off of r series and c l . 40 0 0 25 30 10 5 20 15 20 10 r series v c l pf figure 7. recommended r series vs. capacitive load communications distortion is a key specification in communications applications. intermodulation distortion (imd) is a measure of the ability of an amplifier to pass complex signals without the generation of spurious harmonics. the third order products are usually the most problematic since several of them fall near the fundamen- tals and do not lend themselves to filtering. theory predicts that the third order harmonic distortion components increase in power at three times the rate of the fundamental tones. the specification of third order intercept as the virtual point where fundamental and harmonic power are equal is one standard mea- sure of distortion performance. op amps used in closed-loop applications do not always obey this simple theory. at a gain of two, the ad8002 has performance summarized in figure 8. here the wo rst third order products are plotted versus. input power. the third order intercept of the ad8002 is 33 dbm at 10 mhz. 80 3 7 75 2 1 0 4 56 2 70 65 60 55 50 45 1 third order imd dbc input power dbm 6 845 3 2f 2 f 1 2f 1 f 2 g = +2 f 1 = 10mhz f 2 = 12mhz figure 8. third order imd; f 1 = 10 mhz, f 2 = 12 mhz operation as a video line driver the ad8002 has been designed to offer outstanding perfor- mance as a video line driver. the important specifications of differential gain (0.01%) and differential phase (0.02 ) meet the most exacting hdtv demands for driving one video load with each amplifier. the ad8002 also drives four back-terminated loads (two each), as shown in figure 9, with equally impressive performance (0.01%, 0.07 ). another important consideration is isolation between loads in a multiple load application. the ad8002 has more than 40 db of isolation at 5 mhz when driv- ing two 75 ? back-terminated loads. 750 750 75 cable 75 75 v out #1 v out #2 +v s v s v in 0.1 f 4.7 f 1/2 ad8002 0.1 f 4.7 f 75 cable 75 75 75 cable 75 75 v out #3 v out #4 75 cable 75 75 1/2 ad8002 750 750 75 cable 75 + figure 9. video line driver
rev. d ad8002 C12C driving a-to-d converters the ad8002 is well suited for driving high-speed analog-to- digital converters such as the ad9058. the ad9058 is a dual 8-bit 50 msps adc. in figure 10, the ad8002 is shown driv- ing the inputs of the ad9058 which are configured for 0 v to 2 v ranges. bipolar input signals are buffered, amplified ( 2 ), and offset (by 1.0 v) into the proper input range of the adc. using 0.1 f +v s v s 20 50 1k 18 17 16 15 14 13 12 11 v ref a 10pf clock 5, 9, 22, 24, 37, 41 4,19, 21 25, 27, 42 0.1 f 38 8 v ref b 6 +v int 2 3 +v ref a a in a 549 274 analog in a 0.5v 1.1k ad707 43 +v ref b 20k 0.1 f 2v 1.1k 20k 549 analog in b 0.5v 274 20 0.1 f 40 comp 1 a in b encode a encode b 10 36 encode 74act04 0.1 f +5v 28 29 30 31 32 33 34 35 rz1 rz2 d 0a (lsb) d 7a (msb) d 0b (lsb) d 7b (msb) 7, 20, 26, 39 5v 1n4001 ad9058 (j-lead) rz1, rz2 = 2,000 sip (8-pkg) 74act 273 74act 273 8 8 1/2 ad8002 1/2 ad8002 50 50 figure 10. ad8002 driving a dual a-to-d converter the a d9058 s internal 2 v reference connected to both adcs as shown in figure 10 reduces the number of external compo- nents required to create a complete data acqu isition system. the 20 ? resistors in series with adc inputs are used to help the ad8002s drive the 10 pf adc input capacitance. the ad8002 adds only 100 mw to the power consumption, while not limit- ing the performance of the circuit.
rev. d ad8002 C13C single-ended-to-differential driver using an ad8002 the two halves of an ad8002 can be configured to create a single-ended-to-differential high-speed driver with a 3db band width in excess of 200 mhz, as shown in figure 11. although the individual op amps are each current feedback, the overall architecture yields a circuit with attributes normally associated with voltage feedback amplifiers, while offering the speed advan- tages inherent in current feedback amplifiers. in addition, the gain of the circuit can be changed by varying a single resistor, r f , which is often not possible in a dual op amp differential driver. 50 output #1 50 output #2 r g 511 r f 511 c c 0.5 1.5pf 1/2 ad8002 1/2 ad8002 op amp #1 op amp #2 v in r a 511 r a 511 511 r b 511 r b figure 11. differential line driver the current feedback nature of the op amps, in addition to enabling the wide bandwidth, provides an output drive of more than 3 v p-p into a 20 ? load for each output at 20 mhz. on the other hand, the voltage feedback nature provides symmetrical high impedance inputs and allows the use of reactive compo- nents in the feedback network. the circuit consists of the two op amps, each configured as a unity gain follower by the 511 ? r a feedback resistors between each op amp s output and inverting input. the output of each op amp has a 511 ? r b resistor to the inverting input of the other op amp. thus, each output drives the other op amp through a unity gain inverter configuration. by connecting the two amplifi- ers as cross-coupled inverters, their outputs are freed to be equal and opposite, assuring zero-output common-mode voltage. with this circuit configuration, the common-mode signal of the outputs is reduced. if one output moves slightly higher, the n ega- tive input to the other op amp drives its output to go slightly lower and thus preserves the symmetry of the complementary outputs, which reduces the common-mode signal. the common- mode output signal was measured to be 50 db at 1 mhz. looking at this configuration overall, there are two high imped- ance inputs (the + inputs of each op amp), two low impedance outputs, and high open-loop gain. if we consider the two nonin- verting inputs and just the output of op amp #2, the structure looks like a voltage feedback op amp having two symmetrical, high-impedance inputs, and one output. the +input to op amp #2 is the noninverting input (it has the same polarity as output #2) and the +input to amplifier #1 is the inverting input (oppo- site polarity of output #2). with a feedback resistor r f , an input resistor r g , and grounding of the +input of op amp #2, a feedback amplifier is formed. this configuration is just like a voltage feedback amplifier in an inverting configuration if only output #2 is considered. the addition of output #1 makes the amplifier differential output. the differential gain of this circuit is: g r r r r f g a b =+ ? ? ? ? ? ? 1 the r f /r g term is the gain of the overall op amp configuration and is the same as for an inverting op amp except for the polarity. if output #1 is used as the output referen ce, the gain is posi- tive. the 1 + r a /r b term is the noise gain of each individual op amp in its noninverting configuration. the resulting architecture offers several advantages. first, the gain can be changed by changing a single resistor. changing either r f or r g will change the gain as in an inverting op amp circuit. for most types of differential circuits, more than one resistor must be changed to change gain and still maintain good cmr. reactive elements can be used in the feedback network. this is in contrast to current feedback amplifiers that restrict the use of reactive elements in the feedback. the circuit described requires about 0.9 pf of capacitance in shunt across r f in order to optimize peaking and realize a 3 db bandwidth of more than 200 mhz. the peaking exhibited by the circuit is very sensitive to the value of this capacitor. parasitics in the board layout on the order of tenths of picofarads will influence the frequency response and the value required for the feedback capacitor, so a good lay- out is essential. the shunt capacitor type selection is also critical. a good micro- wave type chip capacitor with high q was found to yield best performance. the part selected for this circuit was a murata erie part number ma280r9b. the distortion was measured at 20 mhz with a 3 v p-p input and a 100 ? load on each output. for output #1 the distortion is 37 dbc and 41 dbc for the second and third harmonics respectively. for output #2 the second harmonic is 35 dbc and the third harmonic is 43 dbc. 6 4 14 1m 10m 1g 100m 6 8 10 12 2 0 2 4 output db frequency hz c c = 0.9pf out+ out figure 12. differential driver frequency response
rev. d ad8002 C14C table i. recommended component values ad8002an (dip) ad8002ar (soic) gain gain component ?0 ? ? +1 +2 +10 +100 ?0 ? ? +1 +2 +10 +100 r f ( ? ) 499 549 576 1210 750 499 1000 499 499 549 953 681 499 1000 r g ( ? ) 49.9 274 576 750 54.9 10 49.9 249 549 681 54.9 10 r bt (nominal) ( ? ) 49.9 49.9 49.9 49.9 49.9 49.9 49.9 49.9 49.9 49.9 49.9 49.9 49.9 49.9 r c ( ? ) * 75 75 0 0 75 75 0 0 r s ( ? ) 49.9 49.9 49.9 49.9 49.9 49.9 r t (nominal) ( ? ) 61.9 54.9 49.9 49.9 49.9 49.9 61.9 54.9 49.9 49.9 49.9 49.9 small signal bw (mhz) 270 380 410 600 500 170 17 250 410 410 600 500 170 17 0.1 db flatness (mhz) 45 80 130 35 60 24 3 50 100 100 35 90 24 3 ad8002arm ( soic) gain component ?0 ? ? +1 +2 +10 +100 r f ( ? ) 499 499 590 1000 681 499 1000 r g ( ? ) 49.9 249 590 681 54.9 10 r bt (nominal) ( ? ) 49.9 49.9 49.9 49.9 49.9 49.9 49.9 r c ( ? ) * 75 75 0 0 r s ( ? ) 49.9 49.9 49.9 r t (nominal) ( ? ) 61.9 49.9 49.9 49.9 49.9 49.9 small signal bw (mhz) 270 400 410 600 450 170 19 0.1 db flatness (mhz) 60 100 100 35 70 35 3 * r c is recommended to reduce peaking, and minimizes input reflections at frequencies above 300 mhz. however, r c is not required. layout considerations the specified high-speed performance of the ad8002 requires careful attention to board layout and component selection. proper r f design techniques and low parasitic component selec- tion are mandatory. the pcb should have a ground plane covering all unused por- tions of the component side of the board to provide a low impedance ground path. the ground plane should be removed from the area near the input pins to reduce stray capacitance. chip capacitors should be used for supply bypassing (see figure 13). one end should be connected to the ground plane and the other within 1/8 in. of each power pin. an additional large tanta- lum electrolytic capacitor (4.7 f 10 f) should be connected in parallel, but not necessarily so close, to supply current for fast, large-signal changes at the output. the feedback resistor should be located close to the inverting input pin in order to keep the stray capacitance at this node to a minimum. capacitance variations of less than 1 pf at the invert- ing input will significantly affect high-speed performance. stripline design techniques should be used for long signal traces (greater than about 1 in.). these should be designed with a characteristic impedance of 50 ? or 75 ? and be properly termi- nated at each end. inverting configuration supply bypassing noninverting configuration r f r bt in +v s v s r s r t r g out c1 0.1 f c3 10 f c2 0.1 f c4 10 f +v s v s r f r bt in +v s v s r t r g out * r c * see table i figure 13. inverting and noninverting configurations
rev. d ad8002 C15C figure 14. board layout (silkscreen)
rev. d ad8002 C16C figure 15. board layout (component layer)
rev. d ad8002 C17C figure 16. board layout (solder side) (looking through the board)
rev. d ad8002 C18C outline dimensions dimensions shown in inches and (mm). 8-lead plastic dip (n-8) seating plane 0.060 (1.52) 0.015 (0.38) 0.210 (5.33) max 0.022 (0.558) 0.014 (0.356) 0.160 (4.06) 0.115 (2.93) 0.070 (1.77) 0.045 (1.15) 0.130 (3.30) min 8 14 5 pin 1 0.280 (7.11) 0.240 (6.10) 0.100 (2.54) bsc 0.430 (10.92) 0.348 (8.84) 0.195 (4.95) 0.115 (2.93) 0.015 (0.381) 0.008 (0.204) 0.325 (8.25) 0.300 (7.62) 8-lead soic (so-8) 85 4 1 0.1968 (5.00) 0.1890 (4.80) 0.2440 (6.20) 0.2284 (5.80) pin 1 0.1574 (4.00) 0.1497 (3.80) 0.0500 (1.27) bsc 0.0688 (1.75) 0.0532 (1.35) seating plane 0.0098 (0.25) 0.0040 (0.10) 0.0192 (0.49) 0.0138 (0.35) 0.0098 (0.25) 0.0075 (0.19) 0.0500 (1.27) 0.0160 (0.41) 8 0 0.0196 (0.50) 0.0099 (0.25) 45 8-lead soic (rm-8) 0.011 (0.28) 0.003 (0.08) 0.028 (0.71) 0.016 (0.41) 33 27 0.120 (3.05) 0.112 (2.84) 85 4 1 0.122 (3.10) 0.114 (2.90) 0.199 (5.05) 0.187 (4.75) pin 1 0.0256 (0.65) bsc 0.122 (3.10) 0.114 (2.90) seating plane 0.006 (0.15) 0.002 (0.05) 0.018 (0.46) 0.008 (0.20) 0.043 (1.09) 0.037 (0.94) 0.120 (3.05) 0.112 (2.84)
rev. d ad8002 C19C location page data sheet changed from rev. c to rev. d. max ratings changed . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 revision history
C20C c01044bC0C4/01(d) printed in u.s.a.

▲Up To Search▲

Price & Availability of AD8002ARZ

	To Download AD8002ARZ Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .